Программа6.3

( параллельный регистр на 4 разряда )

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity reg4 is

port(

data_i: in std_logic_vector(3 downto 0);

clk_i: in std_logic;

ena: in std_logic;

ctrl: in std_logic;

data_out: out std_logic_vector(3 downto 0)

);

end reg4;

architecture arch of reg4 is

signal regist: std_logic_vector(3 downto 0);

begin

process (clk_i)

begin

if(rising_edge(clk_i)) then

if(ena ='1') then

regist <= data_i;

end if;

end if;

end process;

data_out <= regist when ctrl = '1' else "ZZZZ";

end arch;

3. Параллельный регистр на 4 разряда